MC912DG128ACPVE Datasheet, PDF (150/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
I/O Ports with Key Wake-up
11.3 Key Wake-up and port Registers
PORTJ — Port J Register
PORT
KWU
RESET:
Bit 7
PJ7
KWJ7
-
6
PJ6
KWJ6
-
5
PJ5
KWJ5
-
4
PJ4
KWJ4
-
3
PJ3
KWJ3
-
Read and write anytime.
2
PJ2
KWJ2
-
1
PJ1
KWJ1
-
Bit 0
PJ0
KWJ0
-
$0028
PORTH — Port H Register
KWU
RESET:
Bit 7
PH7
KWH7
-
6
PH6
KWH6
-
5
PH5
KWH5
-
4
PH4
KWH4
-
3
PH3
KWH3
-
Read and write anytime.
2
PH2
KWH2
-
1
PH1
KWH1
-
Bit 0
PH0
KWH0
-
$0029
DDRJ — Port J Data Direction Register
RESET:
Bit 7
DDJ7
0
6
DDJ6
0
5
DDJ5
0
4
DDJ4
0
3
DDJ3
0
2
DDJ2
0
1
DDJ1
0
Bit 0
DDJ0
0
$002A
Data direction register J is associated with port J and designates each
pin as an input or output.
Read and write anytime
DDRJ[7:0] — Data Direction Port J
0 = Associated pin is an input
1 = Associated pin is an output
Technical Data
150
MC68HC912DT128A — Rev 4.0
I/O Ports with Key Wake-up
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