MC912DG128ACPVE Datasheet, PDF (141/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupt Control and Priority Registers
Table 10-1. Interrupt Vector Map
Vector Address
Interrupt Source
$FFBC, $FFBD MSCAN 1 errors
$FFBA, $FFBB
$FFB8, $FFB9
$FFB6, $FFB7⁽¹⁾
MSCAN 1 receive
MSCAN 1 transmit
MSCAN 2 wake-up
$FFB4, $FFB5^{(1) MSCAN 2 errors}
$FFB2, $FFB3⁽¹⁾
$FFB0, $FFB1⁽¹⁾
$FF80–$FFAF
MSCAN 2 receive
MSCAN 2 transmit
Reserved
CCR
Mask
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
Local Enable
C1RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
C1RIER (RXFIE)
C1TCR (TXEIE[2:0])
C2RIER (WUPIE)
C2RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
C2RIER (RXFIE)
C2TCR (TXEIE[2:0])
1. MC68HC912DT128A only
HPRIO Value to
Elevate
$BC
$BA
$B8
$B6
$B4
$B2
$B0
$80–$AE
10.6 Interrupt Control and Priority Registers
INTCR — Interrupt Control Register
Bit 7
6
5
4
3
2
IRQE
IRQEN
DLY
0
0
0
RESET:
0
1
1
0
0
0
$001E
1
Bit 0
0
0
0
0
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin
PE1/IRQ).
IRQE can be read anytime and written once in normal modes. In
special modes, IRQE can be read anytime and written anytime,
except the first write is ignored.
IRQEN — External IRQ Enable
The IRQ pin has an internal pull-up.
0 = External IRQ pin is disconnected from interrupt logic.
1 = External IRQ pin is connected to interrupt logic.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Resets and Interrupts
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Technical Data
141