MC912DG128ACPVE Datasheet, PDF (236/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pulse Width Modulator
and then write the counter forcing a new period to start with the new
period value.
Period = Channel-Clock-Period × (PWPER + 1)
Period = Channel-Clock-Period × (2 × PWPER)
(CENTR = 0)
(CENTR = 1)
PWDTYx — PWM Channel Duty Registers
Bit 7
6
5
4
3
2
1
Bit 0
PWDTY0 Bit 7
6
5
4
3
2
1
Bit 0
$0050
PWDTY1 Bit 7
6
5
4
3
2
1
Bit 0
$0051
PWDTY2 Bit 7
6
5
4
3
2
1
Bit 0
$0052
PWDTY3 Bit 7
6
5
4
3
2
1
Bit 0
$0053
RESET:
1
1
1
1
1
1
1
1
Read and write anytime.
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over
or the channel is disabled. Reading this register returns the most
recent value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be
the state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx+1)/(PWPERx+1)] × 100%
Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)] × 100%
(PPOLx = 1)
(PPOLx = 0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx−PWDTYx)/PWPERx] × 100%
Duty cycle = [PWDTYx/PWPERx] × 100%
(PPOLx = 0)
(PPOLx = 1)
Technical Data
236
MC68HC912DT128A — Rev 4.0
Pulse Width Modulator
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