MC912DG128ACPVE Datasheet, PDF (151/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
I/O Ports with Key Wake-up
Key Wake-up and port Registers
DDRH — Port H Data Direction Register
RESET:
Bit 7
DDH7
0
6
DDH6
0
5
DDH5
0
4
DDH4
0
3
DDH3
0
2
DDH2
0
1
DDH1
0
Bit 0
DDH0
0
$002B
Data direction register H is associated with port H and designates each
pin as an input or output. Read and write anytime.
DDRH[7:0] — Data Direction Port H
0 = Associated pin is an input
1 = Associated pin is an output
KWIEJ — Key Wake-up Port J Interrupt Enable Register
RESET:
Bit 7
KWIEJ7
0
6
KWIEJ6
0
5
KWIEJ5
0
4
KWIEJ4
0
3
KWIEJ3
0
2
KWIEJ2
0
1
KWIEJ1
0
Bit 0
KWIEJ0
0
Read and write anytime.
KWIEJ[7:0] — Key Wake-up Port J Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
$002C
KWIEH — Key Wake-up Port H Interrupt Enable Register
RESET:
Bit 7
KWIEH7
0
6
KWIEH6
0
5
KWIEH5
0
4
KWIEH4
0
3
KWIEH3
0
2
KWIEH2
0
1
KWIEH1
0
Bit 0
KWIEH0
0
Read and write anytime.
KWIEH[7:0] — Key Wake-up Port H Interrupt Enables
0 = Interrupt for the associated bit is disabled
1 = Interrupt for the associated bit is enabled
$002D
MC68HC912DT128A — Rev 4.0
MOTOROLA
I/O Ports with Key Wake-up
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Technical Data
151