MC912DG128ACPVE Datasheet, PDF (365/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
18.13.14 msCAN12 Identifier Mask Registers (CIDMR0–7)
The identifier mask register specifies which of the corresponding bits in
the identifier acceptance register are relevant for acceptance filtering.
CIDMR0 R
$0114 W
CIDMR1 R
$0115 W
CIDMR2 R
$0116 W
CIDMR3 R
$0117 W
RESET
CIDMR4 R
$011C W
CIDMR5 R
$011D W
CIDMR6 R
$011E W
CIDMR7 R
$011F W
RESET
Figure 18-16. Identifier Mask Registers (1st bank)
Bit 7
6
5
4
3
2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
-
-
-
-
-
-
Figure 18-17. Identifier Mask Registers (2nd bank)
Bit 7
6
5
4
3
2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
AM6
AM5
AM4
AM3
AM2
AM7
-
AM6
-
AM5
-
AM4
-
AM3
-
AM2
-
1
AM1
AM1
AM1
AM1
-
1
AM1
AM1
AM1
AM1
-
Bit 0
AM0
AM0
AM0
AM0
-
Bit 0
AM0
AM0
AM0
AM0
-
AM7 – AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the
same as its identifier bit, before a match will be detected. The
message will be accepted if all such bits match. If a bit is set, it
indicates that the state of the corresponding bit in the identifier
acceptance register will not affect whether or not the message is
accepted.
0 = Match corresponding acceptance code register and identifier bits.
1 = Ignore corresponding acceptance code register bit.
NOTE: The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
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Technical Data
365