MC912DG128ACPVE Datasheet, PDF (116/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Flash Memory
Freescale Semiconductor, Inc.
8.3 Overview
Each 32K Flash EEPROM array is arranged in a 16-bit configuration and
may be read as either bytes, aligned words or misaligned words. Access
time is one bus cycle for byte and aligned word access and two bus
cycles for misaligned word operations.
The Flash EEPROM module supports bulk erase only.
Each Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and program-
protected 8-Kbyte block for boot routines is located at the top of each 32-
Kbyte array. Since boot programs must be available at all times, the only
useful boot block is at $E000–$FFFF location. All paged boot blocks can
be used as protected program space if desired.
On 0L05H and later mask sets, an optional protection scheme is
supported to protect all four 32-Kbyte Flash EEPROM modules against
accident program or erase. This is achieved using the protection bit
FPOPEN in EEPROM EEMCR (see 8.11 Flash protection bit FPOPEN).
8.4 Flash EEPROM Control Block
A 4-byte register block for each module controls the Flash EEPROM
operation. Configuration information is specified and programmed
independently from the contents of the Flash EEPROM array. At reset,
the 4-byte register section starts at address $00F4 and points to the
00FEE32K register block.
8.5 Flash EEPROM Arrays
After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located
from addresses $4000 to $7FFF and from $C000 to $FFFF. The other
three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and
10FEE32K, are mapped through a 16K byte program page window
located from addresses $8000 to $BFFF. The page window has eight
16K byte pages. The last two pages also map the physical location of the
Technical Data
116
MC68HC912DT128A — Rev 4.0
Flash Memory
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