MC912DG128ACPVE Datasheet, PDF (272/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
PBCTL — 16-Bit Pulse Accumulator B Control Register
BIT 7
6
5
4
3
0
PBEN
0
0
0
RESET:
0
0
0
0
0
$00B0
2
1
BIT 0
0
PBOVI
0
0
0
0
Read or write any time.
16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit
pulse accumulators PAC1 and PAC0.
When PBEN is set, the PACB is enabled. The PACB shares the input pin
with IC0.
PBEN — Pulse Accumulator B System Enable
0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and
PAC0 can be enabled when their related enable bits in
ICPACR ($A8) are set.
1 = Pulse Accumulator B system enabled. The two 8-bit pulse
accumulators PAC1 and PAC0 are cascaded to form the
PACB 16-bit pulse accumulator. When PACB in enabled, the
PACN1 and PACN0 registers contents are respectively the
high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPACR ($A8) have no
effect.
PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
PBOVI — Pulse Accumulator B Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PBOVF is set
PBFLG — Pulse Accumulator B Flag Register
BIT 7
6
5
4
3
0
0
0
0
0
RESET:
0
0
0
0
0
Read or write any time.
$00B1
2
1
BIT 0
0
PBOVF
0
0
0
0
Technical Data
272
MC68HC912DT128A — Rev 4.0
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA