MC912DG128ACPVE Datasheet, PDF (50/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are
pending, processing begins by fetching the normal reset vector
($FFFE:FFFF).
3.4.4 Maskable Interrupt Request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or level-
sensitive triggering is program selectable (INTCR register). IRQ is
always enabled and configured to level-sensitive triggering at reset. It
can be disabled by clearing IRQEN bit (INTCR register). When the MCU
is reset the IRQ function is masked in the condition code register. This
pin is always an input and can always be read. There is an active pull-up
on this pin while in reset and immediately out of reset. The pullup can be
turned off by clearing PUPE in the PUCR register.
Technical Data
50
MC68HC912DT128A — Rev 4.0
Pinout and Signal Descriptions
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