MC912DG128ACPVE Datasheet, PDF (316/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
IBIF — IIC Bus Interrupt Flag
The IBIF bit is set when an interrupt is pending, which will cause a
processor interrupt request provided IBIE is set. IBIF is set when one
of the following events occurs:
1. Complete one byte transfer (set at the falling edge of the 9th
clock).
2. Receive a calling address that matches its own specific address in
slave receive mode.
3. Arbitration lost.
This bit must be cleared by software, writing a one to it, in the interrupt
routine.
RXAK — Received Acknowledge
The value of SDA during the acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates an acknowledge
signal has been received after the completion of 8 bits data
transmission on the bus. If RXAK is high, it means no acknowledge
signal is detected at the 9th clock.
0 = Acknowledge received
1 = No acknowledge received
.
IBDR — IIC Bus Data I/O Register
$00E4
Bit 7
6
5
4
3
2
1
Bit 0
D7
D6
D5
D4
D3
D2
D1
D0
High
RESET:
0
0
0
0
0
0
0
0
Read and write anytime
In master transmit mode, when data is written to the IBDR a data transfer
is initiated. The most significant bit is sent first. In master receive mode,
reading this register initiates next byte data receiving. In slave mode, the
same functions are available after an address match has occurred.
NOTE:
In master transmit mode, the first byte of data written to IBDR following
assertion of MS/SL is used for the address transfer and should comprise
of the calling address (in position D7-D1) concatenated with the required
R/W bit (in position D0).
Technical Data
316
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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