MC912DG128ACPVE Datasheet, PDF (318/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Inter IC Bus
Freescale Semiconductor, Inc.
DDRIB — Data Direction for Port IB Register
RESET:
Bit 7
DDRIB7
0
6
DDRIB6
0
5
DDRIB5
0
4
DDRIB4
0
3
DDRIB3
0
2
DDRIB2
0
1
DDRIB1
0
Bit 0
DDRIB0
0
$00E7
Read and write anytime
DDRIB[7:2]— Port IB [7:2] Data direction
Each bit determines the primary direction for each pin configured as
general-purpose I/O.
0 = Associated pin is a high-impedance input.
1 = Associated pin is an output.
DDRIB[5:0] — These bits served as memory locations since there are
no corresponding external port pins for MC68HC912DT128A.
17.7 IIC Programming Examples
17.7.1 Initialization Sequence
Reset will put the IIC Bus Control Register to its default status. Before
the interface can be used to transfer serial data, an initialization
procedure must be carried out, as follows:
1. Update the Frequency Divider Register (IBFD) and select the
required division ratio to obtain SCL frequency from system clock.
2. Update the IIC Bus Address Register (IBAD) to define its slave
address.
3. Set the IBEN bit of the IIC Bus Control Register (IBCR) to enable
the IIC interface system.
4. Modify the bits of the IIC Bus Control Register (IBCR) to select
Master/Slave mode, Transmit/Receive mode and interrupt enable
or not.
Technical Data
318
MC68HC912DT128A — Rev 4.0
Inter IC Bus
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