MC912DG128ACPVE Datasheet, PDF (83/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Operating Modes
Operating Modes
ESTR — E Clock Stretch Enable
Determines if the E Clock behaves as a simple free-running clock or
as a bus control signal that is active only for external bus cycles.
ESTR is always one in expanded modes since it is required for
address and data de-multiplexing and must follow stretched cycles.
0 = E never stretches (always free running).
1 = E stretches high during external access cycles and low during
non-visible internal accesses (IVIS = 0).
Normal modes: write once; Special modes: write anytime, read
anytime.
IVIS — Internal Visibility
This bit determines whether internal ADDR, DATA, R/W and LSTRB
signals can be seen on the external bus during accesses to internal
locations. In Special Narrow Mode if this bit is set and an internal
access occurs the data will appear wide on Ports A and B. This serves
the same function as the EMD bit of the non-multiplexed versions of
the HC12 and allows for emulation. Visibility is not available when the
part is operating in a single-chip mode.
0 = No visibility of internal bus operations on external bus.
1 = Internal bus operations are visible on external bus.
Normal modes: write once; Special modes: write anytime EXCEPT
the first time. Read anytime.
EBSWAI — Multiplexed External Bus Interface Module Stops in Wait
Mode
This bit controls access to the multiplexed external bus interface
module during wait mode. The module will delay before shutting down
in wait mode to allow for final bus activity to complete.
0 = MEBI continues functioning during wait mode.
1 = MEBI is shut down during wait mode.
Normal modes: write anytime; special modes: write never. Read
anytime.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Operating Modes
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Technical Data
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