MC912DG128ACPVE Datasheet, PDF (444/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Appendix: Changes from MC68HC912DG128
22.2.4 WAIT mode
This new version will correctly exit WAIT mode using short XIRQ or IRQ
inputs.
22.2.5 KWU Filter
The KWU filter will now ignore pulses shorter than 2 microseconds.
22.2.6 Port ADx
Power must be applied to VDDA at all times even if the ADC is not being
used. This is necessary for port AD0 and port AD1 to function correctly
as digital inputs.
22.2.7 ATD
22.2.7.1 Channel Selection
Any channel can be selected for the first conversion of a multiple channel
conversion. Bits CA, CB & CC in ATDxCTL5 do not get masked but are
used to select which channel is used to start the sequential conversion
sequence. For compatibilty, ensure that the appropriate bits are
cleared in the software. See Table 19-8.
Bit CC of ATDxCTL5 is not masked when bit S8CM = 1.
22.2.7.2 CD bit
Bit CD in ATDxCTL5 is renamed SC to differentiate it from extended
functionality of bits CA, CB & CC. Functionality is unchanged as it still
selects conversion from the internal reference sources but when doing a
multiple channel scan, bits CA, CB & CC must be cleared as appropriate
for compatible reference selection.
Technical Data
444
MC68HC912DT128A — Rev 4.0
Appendix: Changes from MC68HC912DG128
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