MC912DG128ACPVE Datasheet, PDF (418/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
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BK1RWE
–
–
–
0
1
1
Table 20-9. Breakpoint Read/Write Control
BK1RW
–
–
–
X
0
1
BK0RWE
0
1
1
–
–
–
BK0RW
X
0
1
–
–
–
Read/Write Selected
R/W is don’t care for full mode or dual mode
BKP0
R/W is write for full mode or dual mode BKP0
R/W is read for full mode or dual mode BKP0
R/W is don’t care for dual mode BKP1
R/W is write for dual mode BKP1
R/W is read for dual mode BKP1
BRKAH — Breakpoint Address Register, High Byte
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
RESET:
0
0
0
0
0
0
$0022
1
Bit 0
9
Bit 8
0
0
These bits are used to compare against the most significant byte of the
address bus.
BRKAL — Breakpoint Address Register, Low Byte
$0023
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
These bits are used to compare against the least significant byte of the
address bus. These bits may be excluded from being used in the match
if BK0ALE = 0.
BRKDH — Breakpoint Data Register, High Byte
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
RESET:
0
0
0
0
0
0
$0024
1
Bit 0
9
Bit 8
0
0
These bits are compared to the most significant byte of the data bus or
the most significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the
breakpoint comparison.
Technical Data
418
MC68HC912DT128A — Rev 4.0
Development Support
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