MC912DG128ACPVE Datasheet, PDF (343/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Clock System
18.10 Clock System
Figure 18-7 shows the structure of the msCAN12 clock generation
circuitry. With this flexible clocking scheme the msCAN12 is able to
handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
SYSCLK
CGM
CLKSRC
msCAN12
CGMCANCLK
Time quanta
Prescaler
clock
(1...64)
EXTALi
CLKSRC
Figure 18-7. Clocking Scheme
The clock source bit (CLKSRC) in the msCAN12 module control register
(CMCR1) (see msCAN12 Bus Timing Register 0 (CBTR0)) defines
whether the msCAN12 is connected to the output of the crystal oscillator
(EXTALi) or to the system clock (SYSCLK).
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met. Additionally, for
high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.
For microcontrollers without the CGM module, CGMCANCLK is driven
from the crystal oscillator (EXTALi).
A programmable prescaler is used to generate out of msCANCLK the
time quanta (Tq) clock. A time quantum is the atomic unit of time handled
by the msCAN12. A bit time is subdivided into three segments⁽¹⁾:
• SYNC_SEG: This segment has a fixed length of one time
quantum. Signal edges are expected to happen within this section.
1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section
10.3.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
For More Information On This Product,
Go to: www.freescale.com
Technical Data
343