MC912DG128ACPVE Datasheet, PDF (288/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Multiple Serial Interface
PF — Parity Error Flag
Indicates if received data’s parity matches parity bit. This feature is
active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCxCR1.
0 = Parity correct
1 = Incorrect parity detected
SC0SR2/SC1SR2 — SCI Status Register 2
$00C5/$00CD
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
RAF
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write has no meaning or effect.
RAF — Receiver Active Flag
This bit is controlled by the receiver front end. It is set during the RT1
time period of the start bit search. It is cleared when an idle state is
detected or when the receiver circuitry detects a false start bit
(generally due to noise or baud rate mismatch).
0 = A character is not being received
1 = A character is being received
If enabled with RIE = 1, RAF set generates an interrupt when
VDDPLL is high while in WAIT mode.
SC0DRH/SC1DRH — SCI Data Register High
$00C6/$00CE
Bit 7
6
5
4
3
2
1
Bit 0
R8
T8
0
0
0
0
0
0
RESET:
—
—
—
—
—
—
—
—
SC0DRL/SC1DRL — SCI Data Register Low
RESET:
Bit 7
R7/T7
—
6
R6/T6
—
5
R5/T5
—
4
R4/T4
—
3
R3/T3
—
2
R2/T2
—
1
R1/T1
—
$00C7/$00CF
Bit 0
R0/T0
—
Technical Data
288
MC68HC912DT128A — Rev 4.0
Multiple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA