MC912DG128ACPVE Datasheet, PDF (358/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
OVRIF — Overrun Interrupt Flag
This bit will be set when a data overrun condition occurred. If not
masked, an Error interrupt is pending while this flag is set.
0 = No data overrun has occurred.
1 = A data overrun has been detected.
RXF — Receive Buffer Full
The RXF flag is set by the msCAN12 when a new message is
available in the foreground receive buffer. This flag indicates whether
the buffer is loaded with a correctly received message. After the CPU
has read that message from the receive buffer the RXF flag must be
handshaked (cleared) in order to release the buffer. A set RXF flag
prohibits the exchange of the background receive buffer into the
foreground buffer. If not masked, a Receive interrupt is pending while
this flag is set.
0 = The receive buffer is released (not full).
1 = The receive buffer is full. A new message is available.
NOTE: The CRFLG register is held in the reset state if the SFTRES bit in
CMCR0 is set.
18.13.7 msCAN12 Receiver Interrupt Enable Register (CRIER)
CRIER R
$0105 W
RESET
Bit 7
WUPIE
0
6
RWRNIE
0
5
TWRNIE
0
4
RERRIE
0
3
TERRIE
0
2
BOFFIE
0
1
OVRIE
0
Bit 0
RXFIE
0
WUPIE — Wake-up Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A wake-up event will result in a wake-up interrupt.
RWRNIE — Receiver Warning Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A receiver warning status event will result in an error interrupt.
TWRNIE — Transmitter Warning Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter warning status event will result in an error
interrupt.
Technical Data
358
MC68HC912DT128A — Rev 4.0
MSCAN Controller
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