MC912DG128ACPVE Datasheet, PDF (182/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Clock Functions
Freescale Semiconductor, Inc.
12.8 Clock Divider Chains
Figure 12-6, Figure 12-7, Figure 12-8, and Figure 12-9 summarize the
clock divider chains for the various peripherals on the
MC68HC912DT128A.
BCSP BCSS
1:x
PHASE
LOCK
LOOP
PLLCLK
SYSCLK
T CLOCK
÷2
GENERATOR
TCLKs
TO CPU
EXTAL
EXTALi
REDUCED
CONSUMPTION
OSCILLATOR
EXTALi
XTAL
EXTALi
BCSP BCSS
0:0
BCSP BCSS
0:1
CLKSRC = 1
CLKSRC = 0
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷2
÷2
E AND P
CLOCK
GENERATOR
ECLK
PCLK
TO
BUSES,
SPI,
PWM,
ATD0, ATD1
MCS = 0
SYNC
MCS = 1
SYNC
CLKSW = 0
CLKSW = 1
TO
MSCAN
TO
MCLK _{SCI0, SCI1,}
ECT
XCLK
TO
RTI, COP
TO CAL
TO BDM
TO CLOCK
MONITOR
Technical Data
182
Figure 12-6. Clock Generation Chain
MC68HC912DT128A — Rev 4.0
Clock Functions
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