MC912DG128ACPVE Datasheet, PDF (297/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Multiple Serial Interface
Serial Peripheral Interface (SPI)
SP0BR — SPI Baud Rate Register
$00D2
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
SPR2
SPR1
SPR0
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Table 16-4. SPI Clock Rate Selection
SPR2
0
0
0
0
1
1
1
1
SPR1
0
0
1
1
0
0
1
1
SPR0
0
1
0
1
0
1
0
1
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at
E Clock = 4 MHz
2.0 MHz
1.0 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
15.6 kHz
Frequency at
E Clock = 8 MHz
4.0 MHz
2.0 MHz
1.0 MHz
500 KHz
250 KHz
125 KHz
62.5 KHz
31.3 KHz
SP0SR — SPI Status Register
$00D3
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Multiple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
Technical Data
297