MC912DG128ACPVE Datasheet, PDF (105/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Bus Control and Input/Output
Registers
PORTA — Port A Register
$0000
Single Chip
RESET:
Expanded
& Periph:
Expanded
narrow
Bit 7
PA7
—
ADDR15/
DATA15
ADDR15/
DATA15/
DATA7
6
PA6
—
ADDR14/
DATA14
ADDR14/
DATA14/
DATA6
5
PA5
—
ADDR13/
DATA13
ADDR13/
DATA13/
DATA5
4
PA4
—
ADDR12/
DATA12
ADDR12/
DATA12/
DATA4
3
PA3
—
ADDR11/
DATA11
ADDR11/
DATA11/
DATA3
2
PA2
—
ADDR10/
DATA10
ADDR10/
DATA10/
DATA2
1
PA1
—
ADDR9/
DATA9
ADDR9/
DATA9/
DATA1
Bit 0
PA0
—
ADDR8/
DATA8
ADDR8/
DATA8/
DATA0
Bits PA[7:0] are associated respectively with addresses ADDR[15:8],
DATA[15:8] and DATA[7:0], in narrow mode. When this port is not
used for external addresses such as in single-chip mode, these pins
can be used as general-purpose I/O. DDRA determines the primary
direction of each pin. This register is not in the on-chip map in
expanded and peripheral modes. Read and write anytime.
DDRA — Port A Data Direction Register
$0002
RESET:
Bit 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
This register determines the primary direction for each port A pin
when functioning as a general-purpose I/O port. DDRA is not in the
on-chip map in expanded and peripheral modes. Read and write
anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
MC68HC912DT128A — Rev 4.0
MOTOROLA
Bus Control and Input/Output
For More Information On This Product,
Go to: www.freescale.com
Technical Data
105