MC912DG128ACPVE Datasheet, PDF (63/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

3.5.14 Port S
3.5.15 Port T
Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Port Signals
Setting the RDPP bit in the PWCTL register configures all port P outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The PWCTL register can be read or written anytime after reset.
Refer to Pulse Width Modulator.
Port S is the 8-bit interface to the standard serial interface consisting of
the two serial communications interfaces (SCI1 and SCI0) and the serial
peripheral interface (SPI) subsystems. Port S pins are available for
general-purpose I/O when standard serial functions are not enabled.
Port S pins serve several functions depending on the various internal
control registers. If WOMS bit in the SC0CR1register is set, the P-
channel drivers of the output buffers are disabled (wire-or mode) for pins
0 through 3. If SWOM bit in the SP0CR1 register is set, the P-channel
drivers of the output buffers are disabled (wire-or mode) for pins 4
through 7. The open drain control affects both the serial and the general-
purpose outputs. If the RDPS bit in the SP0CR2 register is set, Port S
pin drive capabilities are reduced. If PUPS bit in the SP0CR2 register is
set, a pull-up device is activated for each port S pin programmed as a
general purpose input. If the pin is programmed as a general-purpose
output, the pull-up is disconnected from the pin regardless of the state of
PUPS bit. See Multiple Serial Interface.
This port provides eight general-purpose I/O pins when not enabled for
input capture and output compare in the timer and pulse accumulator
subsystem. The TEN bit in the TSCR register enables the timer function.
The pulse accumulator subsystem is enabled with the PAEN bit in the
PACTL register.
Register DDRT determines pin direction of port T when used for general-
purpose I/O. When DDRT bits are set, the corresponding pin is
configured for output. On reset the DDRT bits are cleared and the
corresponding pin is configured for input.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Pinout and Signal Descriptions
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Technical Data
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