MC912DG128ACPVE Datasheet, PDF (282/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Multiple Serial Interface
SC0CR1/SC1CR1 — SCI Control Register 1
Bit 7
6
5
4
LOOPS WOMS
RSRC
M
RESET:
0
0
0
0
3
2
WAKE
ILT
0
0
$00C2/$00CA
1
Bit 0
PE
PT
0
0
Read or write anytime.
LOOPS — SCI LOOP Mode/Single Wire Mode Enable
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the
RXD pin is available as general purpose I/O. The receiver input
is determined by the RSRC bit. The transmitter output is
controlled by the associated DDRS bit. Both the transmitter
and the receiver must be enabled to use the LOOP or the
single wire mode.
If the DDRS bit associated with the TXD pin is set during the LOOPS
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit
associated with the TXD pin is clear during the LOOPS = 1, the TXD
pin becomes high (IDLE line state) for RSRC = 0 and high impedance
for RSRC = 1. Refer to Table 16-2.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TXD and RXD) associated with the SCIx
section.
0 = Pins operate in a normal mode with both high and low drive
capability. To affect the RXD bit, that bit would have to be
configured as an output (via DDRS0/2) which is the single wire
case when using the SCI. WOMS bit still affects general-
purpose output on TXD and RXD pins when SCIx is not using
these pins.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
Technical Data
282
MC68HC912DT128A — Rev 4.0
Multiple Serial Interface
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