MC912DG128ACPVE Datasheet, PDF (363/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Programmer’s Model of Control Registers
18.13.11 msCAN12 Receive Error Counter (CRXERR)
CRXERR R
$010E W
RESET
Bit 7
RXERR7
0
6
RXERR6
0
5
RXERR5
0
4
RXERR4
0
3
RXERR3
0
2
RXERR2
0
1
RXERR1
0
Bit 0
RXERR0
0
This register reflects the status of the msCAN12 receive error counter.
The register is read only.
18.13.12 msCAN12 Transmit Error Counter (CTXERR)
CTXERR R
$010F W
RESET
Bit 7
TXERR7
0
6
TXERR6
0
5
TXERR5
0
4
TXERR4
0
3
TXERR3
0
2
TXERR2
0
1
TXERR1
0
Bit 0
TXERR0
0
This register reflects the status of the msCAN12 transmit error counter.
The register is read only.
NOTE: Both error counters must only be read when in SLEEP or SOFT_RESET
mode.
18.13.13 msCAN12 Identifier Acceptance Registers (CIDAR0–7)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the
next message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied. In the latter case it is required to program the
three last bits (AM2 – AM0) in the mask register CIDMR1 to ‘don’t care’.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
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Technical Data
363