MC912DG128ACPVE Datasheet, PDF (391/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Analog-to-Digital Converter
ATD Registers
the result is available in result register ADR0; CCF1 is set when the
second conversion in a sequence is complete and the result is
available in ADR1, and so forth.
The conversion complete flags are cleared depending on the setting
of the fast flag clear bit (AFFC in ATDCTL2). When AFFC=0, the
status register containing the conversion complete flag must be read
as a precondition before the flag can be cleared. The flag is actually
cleared during a subsequent access to the result register. This
provides a convenient method for clearing the conversion complete
flag when the user is polling the ATD module; it ensures the user is
signaled as to the availability of new data and avoids having to have
the user clear the flag explicitly.
When AFFC=1, the conversion complete flags are cleared when their
associated result registers are read; reading the status register is not
a necessary condition in order to clear them. This is the easiest
method for clearing the conversion complete flags which is useful
when the ATD module signals conversion completion with an
interrupt.
The conversion complete flags are normally read only; in special (test)
mode they can be written.
NOTE: When ATDCTL4/5 register is written, the SCF flags and all CCFx flags
are cleared; any pending interrupt request is canceled.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Analog-to-Digital Converter
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Technical Data
391