MC912DG128ACPVE Datasheet, PDF (189/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Clock Functions
Clock Function Registers
Bit 7
6
5
4
3
2
1
Bit 0
CME
FCME FCMCOP WCOP
DISR
CR2
CR1
CR0
RESET:
0/1
0
0
0
0
1
1
1
Normal
RESET:
0/1
0
0
0
1
1
1
1
Special
COPCTL — COP Control Register
$0016
CME — Clock Monitor Enable
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
0 = Clock monitor is disabled. Slow clocks and stop instruction may
be used.
1 = Slow or stopped clocks (including the stop instruction) will
cause a clock reset sequence or limp-home mode. See Limp-
Home and Fast STOP Recovery modes.
On reset
CME is 1 if VDDPLL is high
CME is 0 if VDDPLL is low.
NOTE:
The VDDPLL-dependent reset operation is not implemented on first
pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or
limp-home mode.
See Limp-Home and Fast STOP Recovery modes.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
Technical Data
189