MC912DG128ACPVE Datasheet, PDF (62/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
3.5.11 Port AD1
This port is an analog input interface to the analog-to-digital subsystem
and used for general-purpose input. When analog-to-digital functions
are not enabled, the port has eight general-purpose input pins,
PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D
function.
Port AD1 pins are inputs; no data direction register is associated with this
port. The port has no resistive input loads and no reduced drive controls.
Refer to Analog-to-Digital Converter.
3.5.12 Port AD0
This port is an analog input interface to the analog-to-digital subsystem
and used for general-purpose input. When analog-to-digital functions
are not enabled, the port has eight general-purpose input pins,
PAD0[7:0]. The ADPU bit in the ATD0CTL2 register enables the A/D
function.
Port AD0 pins are inputs; no data direction register is associated with this
port. The port has no resistive input loads and no reduced drive controls.
Refer to Analog-to-Digital Converter.
3.5.13 Port P
Technical Data
62
The four pulse-width modulation channel outputs share general-purpose
port P pins. The PWM function is enabled with the PWEN register.
Enabling PWM pins takes precedence over the general-purpose port.
When pulse-width modulation is not in use, the port pins may be used for
general-purpose I/O.
Register DDRP determines pin direction of port P when used for
general-purpose I/O. When DDRP bits are set, the corresponding pin is
configured for output. On reset the DDRP bits are cleared and the
corresponding pin is configured for input.
When the PUPP bit in the PWCTL register is set, all input pins are pulled
up internally by an active pull-up device. Pullups are disabled after reset.
MC68HC912DT128A — Rev 4.0
Pinout and Signal Descriptions
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