MC912DG128ACPVE Datasheet, PDF (321/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Inter IC Bus
IIC Programming Examples
be done by setting the transmit acknowledge bit (TXAK) before reading
the 2nd last byte of data. Before reading the last byte of data, a STOP
signal must be generated first. The following is an example showing how
a STOP signal is generated by a master receiver.
MASR
LAMAR
DEC
BEQ
MOVB
DEC
BNE
BSET
ENMASR
NXMAR
BRA
BCLR
MOVB
RTI
RXCNT
ENMASR
RXCNT,D1
D1
NXMAR
IBCR,#$08
NXMAR
IBCR,#$20
IBDR,RXBUF
;DECREASE THE RXCNT
;LAST BYTE TO BE READ
;CHECK SECOND LAST BYTE
;TO BE READ
;NOT LAST OR SECOND LAST
;SECOND LAST, DISABLE ACK
;TRANSMITTING
;LAST ONE, GENERATE ‘STOP’ SIGNAL
;READ DATA AND STORE
17.7.5 Generation of Repeated START
At the end of data transfer, if the master still wants to communicate on
the bus, it can generate another START signal followed by another slave
address without first generating a STOP signal. A program example is
as shown.
RESTART BSET IBCR,#$04
MOVB CALLING,IBDR
ANOTHER START (RESTART)
;TRANSMIT THE CALLING ADDRESS
;D0=R/W
17.7.6 Slave Mode
In the slave interrupt service routine, the module addressed as slave bit
(IAAS) should be tested to check if a calling of its own address has just
been received (see Figure 17-4). If IAAS is set, software should set the
transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the
R/W command bit (SRW). Writing to the IBCR clears the IAAS
automatically. Note that the only time IAAS is read as set is from the
interrupt at the end of the address cycle where an address match
occurred, interrupts resulting from subsequent data transfers will have
IAAS cleared. A data transfer may now be initiated by writing information
to IBDR, for slave transmits, or dummy reading from IBDR, in slave
MC68HC912DT128A — Rev 4.0
MOTOROLA
Inter IC Bus
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Technical Data
321