MC912DG128ACPVE Datasheet, PDF (294/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Multiple Serial Interface
16.5.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
When SPE=1
Figure 16-6. Normal Mode and Bidirectional Mode
Master Mode
MSTR=1
Slave Mode
MSTR=0
Normal
Mode
SPC0=0
Serial Out
MO
SPI
DDRS5
Serial In
MI
SWOM enables open drain output.
Serial In
SI
SPI
DDRS4
Serial Out
SO
SWOM enables open drain output.
Bidirectional
Mode
SPC0=1
Serial Out
SPI
Serial In
DDRS5
MOMI
PS4
SWOM enables open drain output. PS4 becomes GPIO.
Serial In
SPI
Serial Out
DDRS4
PS5
SISO
SWOM enables open drain output. PS5 becomes GPIO.
16.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes.
SP0CR1 — SPI Control Register 1
RESET:
Bit 7
SPIE
0
6
SPE
0
5
SWOM
0
4
MSTR
0
3
CPOL
0
2
CPHA
1
1
SSOE
0
Bit 0
LSBF
0
$00D0
Read or write anytime.
SPIE — SPI Interrupt Enable
0 = SPI interrupts are inhibited
Technical Data
294
MC68HC912DT128A — Rev 4.0
Multiple Serial Interface
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA