MC912DG128ACPVE Datasheet, PDF (149/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Technical Data — MC68HC912DT128A
Section 11. I/O Ports with Key Wake-up
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.3 Key Wake-up and port Registers . . . . . . . . . . . . . . . . . . . . . . 150
11.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
11.2 Introduction
The offers 16 additional I/O ports with key wake-up capability.
The key wake-up feature of the MC68HC912DT128A issues an interrupt
that will wake up the CPU when it is in the STOP or WAIT mode. Two
ports are associated with the key wake-up function: port H and port J.
Port H and port J wake-ups are triggered with either a rising or falling
signal edge. For each pin which has an interrupt enabled, there is a path
to the interrupt request signal which has no clocked devices when the
part is in stop mode. This allows an active edge to bring the part out of
stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFH or KWIFJ register and
its corresponding KWIEH or KWIEJ bit are both set. All 16 bits/pins share
the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes.
MC68HC912DT128A — Rev 4.0
MOTOROLA
I/O Ports with Key Wake-up
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Technical Data
149