MC912DG128ACPVE Datasheet, PDF (109/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Bus Control and Input/Output
Registers
In peripheral mode, the PEAR register is not accessible for reads or
writes. However, the CGMTE control bit is reset to one to configure
PE6 as a test output for the CGM module.
NDBE — No Data Bus Enable
Normal: write once; Special: write anytime EXCEPT the first. Read
anytime.
0 = PE7 is used for DBE, external control of data enable on
memories, or inverted E clock.
1 = PE7 is CAL function if CALE bit is set in PEAR register or
general-purpose I/O otherwise.
The NDBE bit has no effect in Single Chip or Peripheral Modes and
PE7 is defaulted to the CAL function if CALE bit is set in PEAR
register or to an I/O otherwise.
CGMTE — Clock Generator Module Testing Enable
Normal: write never; Special: write anytime EXCEPT the first time.
Read anytime.
0 = PE6 is general-purpose I/O or pipe output.
1 = PE6 is a test signal output from the CGM module (no effect in
single chip or normal expanded modes). PIPOE = 1 overrides
this function and forces PE6 to be a pipe status output signal.
PIPOE — Pipe Status Signal Output Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime.
0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test
output signal from the CGM module).
1 = PE[6:5] are outputs and indicate the state of the instruction
queue (only effective in expanded modes).
NECLK — No External E Clock
Normal single chip: write once; special single chip: write anytime; all
other modes: write never.
Read anytime. In peripheral mode, E is an input and in all other
modes, E is an output.
MC68HC912DT128A — Rev 4.0
MOTOROLA
Bus Control and Input/Output
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Technical Data
109