MC912DG128ACPVE Datasheet, PDF (335/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
MSCAN Controller
Interrupts
three bits in the identifier acceptance control register (see msCAN12
Identifier Acceptance Control Register (CIDAC)). These identifier hit
flags (IDHIT2–0) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the
cause of the receiver interrupt. In case that more than one hit occurs (two
or more filters match) the lower hit has priority.
A hit will also cause a receiver interrupt if enabled.
18.6 Interrupts
The msCAN12 supports four interrupt vectors mapped onto eleven
different interrupt sources, any of which can be individually masked (for
details see msCAN12 Receiver Flag Register (CRFLG) to msCAN12
Transmitter Control Register (CTCR)):
• Transmit interrupt: At least one of the three transmit buffers is
empty (not scheduled) and can be loaded to schedule a message
for transmission. The TXE flags of the empty message buffers are
set.
• Receive interrupt: A message has been successfully received and
loaded into the foreground receive buffer. This interrupt will be
emitted immediately after receiving the EOF symbol. The RXF flag
is set.
• Wake-up interrupt: An activity on the CAN bus occurred during
msCAN12 internal SLEEP mode.
• Error interrupt: An overrun, error or warning condition occurred.
The receiver flag register (CRFLG) will indicate one of the
following conditions:
– Overrun: an overrun condition as described in Receive
Structures has occurred.
– Receiver warning: the receive error counter has reached the
CPU warning limit of 96.
– Transmitter warning: the transmit error counter has reached
the CPU warning limit of 96.
MC68HC912DT128A — Rev 4.0
MOTOROLA
MSCAN Controller
For More Information On This Product,
Go to: www.freescale.com
Technical Data
335