MC912DG128ACPVE Datasheet, PDF (406/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

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is temporary storage for BDM commands.The CCRSAV register
preserves the content of the CPU12 CCR while BDM is active.
The only registers of interest to users are the STATUS register and the
CCRSAV register.The other BDM registers are only used by the BDM
firmware to execute commands.The registers are accessed by means of
the hardware READ_BD and WRITE_BD commands, but should not be
written during BDM operation (except the CCRSAV register which could
be written to modify the CCR value).
20.4.5.1 STATUS
The STATUS register is read and written by the BDM hardware as a
result of serial data shifted in on the BKGD pin.
Read: all modes.
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the
INSTRUCTION register is a one. A user would never write ones to bits
3 through 5 because these bits are only used by BDM firmware.
STATUS— BDM Status Register⁽¹⁾
BIT 7
6
5
4
3
2
1
ENBDM BDMACT ENTAG
SDV
TRACE CLKSW
-
RESET:
0
1
0
0
0
0
0
(NOTE 1)
RESET:
0
0
0
0
0
0
0
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.
BIT 0
-
0
0
$FF01
Special Single
Chip & Periph
All other modes
ENBDM — Enable BDM (permit active background debug mode)
0 = BDM cannot be made active (hardware commands still
allowed).
1 = BDM can be made active to allow firmware commands.
BDMACT — Background Mode Active Status
Technical Data
406
MC68HC912DT128A — Rev 4.0
Development Support
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