MC912DG128ACPVE Datasheet, PDF (256/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
TCTL3 — Timer Control Register 3
Bit 7
6
5
EDG7B EDG7A EDG6B
RESET:
0
0
0
TCTL4 — Timer Control Register 4
Bit 7
6
5
EDG3B EDG3A EDG2B
RESET:
0
0
0
4
EDG6A
0
4
EDG2A
0
3
EDG5B
0
3
EDG1B
0
2
EDG5A
0
2
EDG1A
0
1
EDG4B
0
1
EDG0B
0
Bit 0
EDG4A
0
Bit 0
EDG0A
0
$008A
$008B
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Table 15-2. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
TMSK1 — Timer Interrupt Mask 1
$008C
Bit 7
6
5
4
3
2
1
Bit 0
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status
register. If cleared, the corresponding flag is disabled from causing a
hardware interrupt. If set, the corresponding flag is enabled to cause a
hardware interrupt.
Read or write anytime.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.
Technical Data
256
MC68HC912DT128A — Rev 4.0
Enhanced Capture Timer
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