MC912DG128ACPVE Datasheet, PDF (259/478 Pages) Freescale Semiconductor, Inc – Upward compatible with M68HC11 instruction set

Freescale Semiconductor, Inc.
Enhanced Capture Timer
Timer Register Descriptions
TFLG2 — Main Timer Interrupt Flag 2
$008F
Bit 7
6
5
4
3
2
1
Bit 0
TOF
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
TFLG2 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, set the bit to one.
Read anytime. Write used in clearing mechanism (set bits cause
corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR
register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
TC0 — Timer Input Capture/Output Compare Register 0
Bit 7
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
Bit 7
6
5
4
3
2
1
TC1 — Timer Input Capture/Output Compare Register 1
Bit 7
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
Bit 7
6
5
4
3
2
1
TC2 — Timer Input Capture/Output Compare Register 2
Bit 7
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
Bit 7
6
5
4
3
2
1
TC3 — Timer Input Capture/Output Compare Register 3
Bit 7
6
5
4
3
2
1
Bit 15
14
13
12
11
10
9
Bit 7
6
5
4
3
2
1
MC68HC912DT128A — Rev 4.0
MOTOROLA
Enhanced Capture Timer
For More Information On This Product,
Go to: www.freescale.com
$0090–$0091
Bit 0
Bit 8
Bit 0
$0092–$0093
Bit 0
Bit 8
Bit 0
$0094–$0095
Bit 0
Bit 8
Bit 0
$0096–$0097
Bit 0
Bit 8
Bit 0
Technical Data
259