F81867 Datasheet, PDF (99/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
In order to achieve the lower power consumption, F81867 provides the ERP_CTRL1# to turn off the
V3A so that the system can enter the Fintek G3’ state.
The block diagram below shows how the connection and control method for F81867 and PCH.
5VSB
ATX Power
VCC
V5A
ERP_CTRL0#
(SLP_SUS_FET)
3.3V VSB VR
5VSB
ERP_CTRL1#
5VDUAL
3VSB
V3A
5VDUAL
V3A
SUSWARN#
SUSACK#
CPT PCH
DPWROK
RSMRST#
SUS_WARN#
SUS_ACK#
SLP_SUS#
5VA_PWOK#
RSMRST#
1.05V
SUS_WARN#
V Detect & Delay
F81867
Fig 6-17
MB Logic
5VDUAL
Control
SUS_WARN
(Invert From PCH)
S0 State
ERP_CTRL0#
ERP_CTRL1#
V5A
3VSB
I_3VSB
S3 State
S4/S5
DSW
G3’
G3
The register for setting this mode is at CR0A, index 0xEC [7:6]. When choose Intel DSW mode,
ERP_CTRL0#, & ERP_CTRL1# would follow SLP_SUS#. When choose Intel DSW + Fintek G3’ mode,
ERP_CTRL0# would follows SLP_SUS#, & ERP_CTRL1# will enter Fintek ERP mode after entering DSW
mode for 6.4s (default, the time is programmable).
In sum, there are three blocks in this mode (Please refer to the application circuit for the HW schematic):
a. DSW Control Block:
a-1 SLP_SUS#: SIO input pin from CPT PCH SLP_SUS#.
a-2 SUS_WARN#: SIO input pin from CPT PCH SUS_WARN#.
a-3 SUS_ACK#: SIO output pin to CPT PCH SUSACK#.
a-4 DPWROK: SIO output pin to CPT PCH DPWROK.
b. ERP Control Block:
b-1 ERP_CTRL0#: Support “CPT PCH DSW” control mode which is a low active signal to turn on/off
3VSB/5VSB power source by P MOSFET.
b-2 ERP_CTRL1#: Support “Fintek G3’ ” control mode which is a low active signal to turn on/off
3VA/5VA power source by P MOSFET.
99
Dec, 2011
V0.12P