F81867 Datasheet, PDF (24/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

SDA
I_lv/OD_{16st, 5v}
F81867
I2C Interface DATA pin. AMD TSI & Intel PCH
(IBX Peak) data pin.
5.8 ACPI, ERP
Pin
Pin Name
Type
PWR
Description
Standby power rail control pin 0. This pin controls an
external PMOS to turn on or off the standby power
ERP_CTRL0#
52
OD_12,5V
I_VSB3V ^rail.
In the S5 state, the default is set to 1 to cut off the
standby power rail.
GPIO00
I/OOD_12st,5v
General purpose IO.
Standby power rail control pin 1. This pin controls an
external PMOS to turn on or off the standby power
ERP_CTRL1#
53
OD_12,5V
I_VSB3V ^rail.
In the S5 state, the default is set to 1 to cut off the
standby power rail.
GPIO01
I/OOD_12st,5v
General purpose IO.
This pin asserts low when the PCH is planning to
SUS_WARN#
54
enter the DSW power state. It can detect 5VDUAL
IN_st
I_VSB3V level with delay setting supported. The delay time is
1ms~8S (default 4s)
GPIO02
I/OOD_12st,5v
General purpose IO.
SUS_ACK#
55
OD_12,5v
This pin must wait SUSWARN# signal for entering
I_VSB3V DSW power state.
GPIO03
I/OOD_12st,5v
General purpose IO.
This pin asserts low which comes from PCH to shut
SLP_SUS#
56
IN_st,lv
off suspend power rails externally to enhance power
I_VSB3V _{saving function.}
GPIO04
I/OOD_12st,5v
General purpose IO.
GPIO05
I/OOD_12st,5v
General purpose IO.
57
SOUT5
I_VSB3V _{UART Serial Output. Used to transmit serial data out to}
O₁₂
the communication link.
GPIO06
I/OOD_12st,5v
General purpose IO.
58
SIN5
IN_t,5v
I_VSB3V _{UART Serial Input. Used to receive serial data}
through the communication link.
GPIO07
I/OOD_12st,5v
General purpose IO.
59
RTS5#
UART Request To Send. An active low signal informs
I_VSB3V
O₁₂
the modem or data set that the controller is ready to
send data.
65
GPIO10
I/OOD_{12st,5v I_VSB3V} General purpose IO.
LED_VSB
OOD_12,5V
Power LED for VSB.
66
GPIO11
I/OOD_{12st,5v I_VSB3V} General purpose IO.
LED_VCC
OOD_12,5V
Power LED for VCC.
I2C Interface CLOCK pin. Clock output for AMD TSI
67
SCL
I_lv/OD_{12st, 5v} I_VSB3V _{& Intel PCH (IBX Peak).}
24
Dec, 2011
V0.12P