F81867 Datasheet, PDF (210/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
0: μC and peripherals are reset by 5VSB power on reset, μC watchdog
timerout reset and Debug port exit reset.
0
EC_GRST
R/W 5VSB 0
1: μC and peripherals are reset by 5VSB power on reset and Debug port exit
reset.
WDT Reset Gate 1 Register ⎯ Offset 05h
Bit
Name
R/W Reset Default
Description
7 SMFI_WD_RST_DIS R/W 5VSB
0: SMFI will reset by μC watchdog timeout.
1
1: SMFI won’t be reset by μC watchdog timeout.
6-5
Reserved
-
-
- Reserved.
4 INTC_WD_RST_DIS R/W 5VSB
0: INTC will reset by μC watchdog timeout.
1
1: INTC won’t be reset by μC watchdog timeout.
3-2
Reserved
-
-
- Reserved.
1 CIR_WD_RST_DIS R/W 5VSB
0: CIR will reset by μC watchdog timeout.
1
1: CIR won’t be reset by μC watchdog timeout.
0 PWM_WD_RST_DIS R/W 5VSB
0: PWM will reset by μC watchdog timeout.
1
1: PWM won’t be reset by C watchdog timeout.
WDT Reset Gate 2 Register ⎯ Offset 06h
Bit
Name
R/W _Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3 ACPI_WD_RST_DIS R/W _5VSB
0: ACPI will reset by μC watchdog timeout.
1
1: ACPI won’t be reset by μC watchdog timeout.
2 KBC_WD_RST_DIS R/W _5VSB
0: KBC will reset by μC watchdog timeout.
1
1: KBC won’t be reset by μC watchdog timeout.
1 GPIO_WD_RST_DIS R/W _5VSB
0: GPIO will reset by μC watchdog timeout.
1
1: GPIO won’t be reset by μC watchdog timeout.
0 CFG_WD_RST_DIS R/W _5VSB
0: CFG will reset by μC watchdog timeout.
1
1: CFG won’t be reset by μC watchdog timeout
RTC RAM Write Protect Register ⎯ Offset 06h
Bit
Name
R/W _Reset Default
Description
7 RTC_WR_DIS_7 R/W _5VSB
Set “1” to enable write protect for RTC RAM index
0
0xF0 ~ 0xFF.
6 RTC_WR_DIS_6 R/W _5VSB
Set “1” to enable write protect for RTC RAM index
0
0xE0 ~ 0xEF.
5 RTC_WR_DIS_5 R/W _5VSB
Set “1” to enable write protect for RTC RAM index
0
0xD0 ~ 0xDF.
210
Dec, 2011
V0.12P