F81867 Datasheet, PDF (287/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

2
PME_N_IN
R
-
1 ERP_CTRL1_IN R
-
0 ERP_CTRL0_IN R
-
0 ^{Pin status of PME#.}
0 ^{Pin status of ERP_CTRL1#.}
0 ^{Pin status of ERP_CTRL0#.}
ACPI Pin Status 2 Register ⎯ Offset 04h
Bit
Name
R/W Reset Default
7
Reserved
-
-
- Reserved.
6
LRESET_N_IN
R
-
- ^{Pin status of LRESET#.}
Description
5
VSB3VOK
R
-
0 ^{The VSB3V power is ready.}
4
VDD3VOK
R
-
0 ^{The VDD3V power is ready.}
3
S5_N_IN
R
-
0 ^{Pin status of S5#.}
2
S3_N_IN
R
-
0 ^{Pin status of S3#.}
1
PWSIN_N_IN
R
-
0 ^{Pin status of PWSIN#.}
0
ATXPG_IN
R
-
0 ^{Pin status of ATXPG.}
F81867
ACPI Pin Status 3 Register ⎯ Offset 05h
Bit
Name
R/W Reset Default
7-4
Reserved
-
-
- Reserved.
3
DPWROK_IN
R
-
0 ^{Pin status of DPWROK.}
2 SUS_ACK_N_IN R
-
0 ^{Pin status of SUS_ACK#.}
1 SUS_WARN_N_IN R
-
0 ^{Pin status of SUS_WARN#.}
0 SLP_SUS_N_IN R
-
0 ^{Pin status of SLP_SUS.}
Description
ACPI Input Pin Control 1 Register ⎯ Offset 07h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3
μC_ATXPG
R/W 5VSB 1 ^{μC control this bit to and-ed with ATXPG pin for internal ATXPG signal.}
2
μC_S3_N
R/W 5VSB 1 ^{μC control this bit to and-ed with S3# pin for internal S3# signal.}
1
μC_S5_N
R/W 5VSB 1 ^{μC control this bit to and-ed with S5# pin for internal S5# signal.}
0
μC_PWSIN_N R/W 5VSB 1 μC control this bit to and-ed with PWSIN# pin for internal PWSIN# signal.
ACPI Input Pin Control 2 Register ⎯ Offset 08h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved.
1 μC_SUS_WARN_N R/W 5VSB
1
μC control this bit to and-ed with SUS_WARN# pin for internal SUS_WARN#
signal.
0
μC_SLP_SUS_N R/W 5VSB
1
μC control this bit to and-ed with SLP_SUS# pin for internal SLP_SUS#
signal.
287
Dec, 2011
V0.12P