F81867 Datasheet, PDF (299/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
CIR – Waveform Logic 0 Count Register – Index 2308h
Bit
Name
R/W Reset Default
Description
7-0
WaveL_Count R/W 5VSB 02h The registers of WaveL_Count indicate RX logic 0 count number
CIR – Rx Protocol Register – Index 2309h
Bit
Name
R/W Reset Default
Description
7
Low_Frequency R/W 5VSB
1b
Write 1 to indicate RX carry frequency from 20k to 100k, and write 0 to
indicate RX carry frequency from 400k to 500k.
6-5
Reserved
-
-
0h Reserved
4
RXINV
R/W 5VSB 1b Write 1 to indicate invert RX input, or to indicate by pass RX.
Write 1 to indicate RX input is demodulation , or to indicate RX is
3
Bypass
R/W 5VSB 1b
un-demodulation.
000 : ITT
001 : NEC
010 : NOKIA
2-0
Protocol
R/W 5VSB 1h
011 : SHARP
100 : SONY
101 : PHILIPS RC5
7.20.16 Debug Port μC Side Register (Base Address 0x3200, 256 bytes)
These registers are accessed by the host debug port interface, μC can’t access these register.
Debug Port Control Register ⎯ Offset 00h
Bit
Name
R/W Reset Default
Description
7
SOFT_RST
W 5VSB 0 Debug Port asserts a software reset to μC.
6-4
Reserved
-
-
- Reserved
3 ^{DBPORT_EXIT_RST} R/W 5VSB
_EN
0 ^{Set “!” to enable reset μC after exit debug mode.}
2 DBPORT_STEP W 5VSB 0 Write “1” to trigger a single step.
1
DBPORT_NEXT_BR
K
W
5VSB
0 Write “1” to force μC run to next break point.
0 ^{DBPORT_FREE_RU} R/W 5VSB
N
0: μC will stop when entering into the debug mode.
0
1: μC is free run.
Break Point Select Register ⎯ Offset 01h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
- Reserved
00: Select break point 0 to access.
01: Select break point 1 to access.
1-0 BRK_PTR_SEL R/W -5VSB 00h
10: Select break point 2 to access.
11: Select break point 3 to access.
299
Dec, 2011
V0.12P