F81867 Datasheet, PDF (175/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7.9 WDT Registers (CR07)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
WDT Device Enable Register
60
Base Address High Register
61
Base Address Low Register
F5
WDT Control Register
F6
WDT Timer Register
FA
WDT PME Enable Register
F81867
MSB
--
00
00
00
00
00
Default Value
----
0000
0000
0000
0000
01
--
LSB
-0
00
00
00
00
-0
WDT Device Base Address Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
0 Reserved
0: disable WDT base address.
0
WDT_EN
R/W 5VSB 0
1: enable WDT base address.
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W 5VSB 00h The MSB of WDT base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W 5VSB 00h The LSB of WDT base address.
Watchdog Control Configuration Register 1 ⎯ Index F5h
Bit
Name
R/W Reset Default
Description
7
Reserved
R
-
0 ^Reserved
If watchdog timeout event occurred, this bit will be set to 1. Write a 1 to this
6
WDTMOUT_STS R/W 5VSB
0 _{bit will clear it to 0.}
5
WD_EN
R/W 5VSB 0 ^{If this bit is set to 1, the counting of watchdog time is enabled.}
4
WD_PULSE
R/W 5VSB 0 ^{Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.}
3
WD_UNIT
R/W 5VSB 0 ^{Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.}
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
2
WD_HACTIVE R/W 5VSB
0 _{this bit.}
Select output pulse width of RSTOUT#
1-0 WD_PSWIDTH R/W 5VSB 0 0: 1 ms
1: 25 ms
2: 125 ms
3: 5 sec
Watchdog Timer Configuration Register 2 ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
7-0
WD_TIME
R/W 5VSB 0 ^{Time of watchdog timer (0~255)}
175
Dec, 2011
V0.12P