F81867 Datasheet, PDF (238/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
FAN Interrupt Status Register ⎯ Offset 91h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
R
-
0 Reserved
This bit is set when the fan3 count exceeds the count limit.
2
FAN3_STS
R/W 3VCC
--
Write 1 to clear this bit, write 0 will be ignored.
This bit is set when the fan2 count exceeds the count limit.
1
FAN2_STS
R/W 3VCC
--
Write 1 to clear this bit, write 0 will be ignored.
This bit is set when the fan1 count exceeds the count limit.
0
FAN1_STS
R/W 3VCC
--
Write 1 to clear this bit, write 0 will be ignored.
FAN Real Time Status Register ⎯ Offset 92h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
--
-
0 Reserved
2
FAN3_EXC
R 3VCC
This bit set to high mean that fan3 count can’t meet expect count
-- over than SMI time(CR9F) or when duty not zero but fan stop
over then 3 sec.
1
FAN2_EXC
R 3VCC
This bit set to high mean that fan2 count can’t meet expect count
-- over than SMI time(CR9F) or when duty not zero but fan stop
over then 3 sec.
0
FAN1_EXC
R 3VCC
This bit set to high mean that fan1 count can’t meet expect count
-- over than SMI time(CR9F) or when duty not zero but fan stop
over then 3 sec.
FAN BEEP# Enable Register ⎯ Offset 93h
Bit
Name
R/W Reset Default
7
Reserved
-
-
- Reserved
Description
FULL_WITH_
Set one will enable FAN to force full speed when T2 over high
6
R/W 5VSB
0
T2_EN
limit.
FULL_WITH_
Set one will enable FAN to force full speed when T1 over high
5
R/W 5VSB
0
T1_EN
limit.
4
Reserved
-
-
- Reserved
3
Reserved
-
-
- Reserved.
2 EN_FAN3_ BEEP R/W 5VSB
0 A one enables the corresponding interrupt status bit for BEEP.
1 EN_FAN2_ BEEP R/W 5VSB
0 A one enables the corresponding interrupt status bit for BEEP.
0 EN_FAN1_ BEEP R/W 5VSB
0 A one enables the corresponding interrupt status bit for BEEP.
238
Dec, 2011
V0.12P