F81867 Datasheet, PDF (192/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

2
Reserved
-
-
- Reserved.
Select the FIFO depth.
00: 16-byte FIFO.
1-0
FIFO_MODE
R/W LRESET# 00h 01: 32-byte FIFO.
10: 64-byte FIFO.
11: 128-byte FIFO.
F81867
7.15 UART2 Registers (CR11)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
Device Enable Register
60
Base Address High Register
61
Base Address Low Register
F0
IRQ Share Register
F2
Clock Select Register
F4
9bit-mode Slave Address Register
F5
9bit-mode Slave Address Mask Register
F0
IRQ Share Register
F6
FIFO Mode Register
MSB
--
00
11
--
00
--
00
00
00
Default Value
----
0000
1110
- - 00
00- -
----
0000
0000
000 -
LSB
-1
10
00
11
00
00
00
00
00
UART 2 Device Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0: disable UART 2 I/O Port.
0
UART2_EN
R/W LRESET# 1
1: enable UART 2 I/O Port.
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 02h The MSB of UART 2 base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-1 BASE_ADDR_LO R/W LRESET# F8h The LSB of UART 2 base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELUR12RQ
R/W LRESET# 3h Select the IRQ channel for UART 2.
192
Dec, 2011
V0.12P