F81867 Datasheet, PDF (223/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
I2C Command Byte/TSI Command Byte – Offset EDh
Bit
Name
R/W Reset Default
Description
There are actual two bytes for this Offset. TSI_CMD_PROG
select which byte to be programmed:
0: I2C_CMD, which is the command code for write byte/word,
7-0 I2C_CMD/TSI_CMD R/W 5VSB 0/1 read byte/word, block write/read and process call protocol.
1: TSI_CMD, which is the command code for Intel temperature
interface block read protocol and the data byte for AMD TSI send
byte protocol.
I2C Status – Offset EEh
Bit
Name
R/W Reset Default
Description
Set 1 to pending auto TSI accessing. (In AMD model, auto
accessing will issue a send-byte followed a receive-byte; In Intel
7
TSI_PENDING
R/W LRESET#
0
model, auto accessing will issue a block read).
To use the SCL/ SDA as a I2C master, set this bit to “1” first.
6 TSI_CMD_PROG R/W 5VSB 0 Set 1 to program TSI_CMD.
Kill the current I2C transfer and return the state machine to idle. It
5
PROC_KILL
R/W 5VSB
0
will set an fail status if the current transfer is not completed.
This is set when PROC_KI LL kill an un-completed transfer. It will
4
FAIL_STS
R 5VSB
0
be auto cleared by next I2C transfer.
This is the arbitration lost status if a I2C command is issued. Auto
3
I2C_ABT_ERR
R 5VSB
0
cleared by next I2C command.
This is the timeout status if a I2C command is issued. Auto
2
I2C_TO_ERR
R 5VSB
0
cleared by next I2C command.
This is the NACK error status if a I2C command is issued. Auto
1
I2C_NAC_ERR
R 5VSB
0
cleared by next I2C command.
0: a I2C transfer is in process.
0
I2C_READY
R 5VSB
1
1: Ready for next I2C command.
I2C Protocol Select – Offset EFh
Bit
Name
R/W Reset Default
Description
Write “1” to trigger a I2C transfer with the protocol specified by
7
I2C_START
W
-
0
SMB_PROTOCOL.
6-4
Reserved
-
-
- Reserved.
223
Dec, 2011
V0.12P