F81867 Datasheet, PDF (113/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
MODEM Status Register (MSR) ⎯ Base + 6
Bit
Name
R/W Reset Default
Description
7
DCD
R
-
- ^{Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2}
in MCR.
6
RI
R
-
-
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
5
DSR
R
-
- ^{Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in}
MCR
4
CTS
R
-
-
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
0: No state changed at DCD#.
3
DDCD
R LRESET# 0 _{1: State changed at DCD#.}
2
TERI
R LRESET#
0
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1
DDSR
R LRESET# 1 _{1: State changed at DSR#.}
0
DCTS
R LRESET#
1
0: No state changed at CTS#.
1: State changed at CTS#.
Scratch Register ⎯ Base + 7
Bit
Name
R/W Reset Default
7-0
SCR
R/W LRESET# 00h Scratch register.
Description
113
Dec, 2011
V0.12P