F81867 Datasheet, PDF (176/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

F81867
Watchdog PME Enable Configuration Register 2 ⎯ Index FAh
Bit
Name
R/W Reset Default
Description
0: No WDT PME occurred.
7
WDT_PME
R 5VSB 0 1: WDT PME occurred.
The WDT PME is occurred one unit before WDT timeout.
6
WDT_PME_EN R/W 5VSB
0
0: Disable Watchdog PME.
1: enable Watchdog PME.
5
Reserved
R
-
0 ^Reserved
WDT Clock Source Select
4
WDT_CLK_SEL R/W 5VSB 1 0: Internal 1KHz clock.
1: 1KHZ clock driven by CLKIN.
3-1
Reserved
R
-
0 ^Reserved
0
WDOUT_EN
R/W 5VSB
0
0: disable Watchdog time out output via WDTRST#.
1: enable Watchdog time out output via WDTRST#.
7.10 PME, ACPI and EUP Registers (LDN 0x0A)
“-“ Reserved or Tri-State
Register 0x[HEX]
Register Name
30
PME Device Enable Register
F0
PME Event Enable 1 Register
F1
PME Event Status 1 Register
F2
PME Event Enable 2 Register
F3
PME Event Status 2 Register
F4
ACPI Control Register 1
F5
ACPI Control Register 2
F6
ACPI Control Register 3
F8
LED Control Register 1
F9
LED Control Register 2
FA
LED Control Register 3
FC
DSW Delay Register
FE
RI De-bounce Select Register
E0
ERP Enable Register
E1
ERP Control Register 1
E2
ERP Control Register 2
E3
ERP PWSIN De-bounce Register
E4
ERP RSMRST De-bounce Register
E5
ERP PWSOUT Pulse Register
E6
ERP PSON De-bounce Register
E7
ERP Deep S5 Delay Register
E8
ERP Wakeup Enable Register
MSB
--
00
--
00
--
--
-0
0-
-0
-0
--
--
0 0-
--
10
-0
00
00
11
00
01
0-
Default Value
----
0000
----
0000
----
0001
0111
- 00 -
0000
00- 0
- - 01
----
----
0011
0000
0000
0100
0010
0001
0100
1000
0100
LSB
-0
00
--
00
--
11
--
--
00
00
11
00
00
00
0-
00
11
01
11
11
11
00
176
Dec, 2011
V0.12P