F81867 Datasheet, PDF (119/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

7. Register Description
F81867
The configuration register is used to control the behavior of the corresponding devices. To configure the register,
using the index port to select the index and then writing data port to alter the parameters. The default index port and
data port are 0x4E and 0x4F respectively. Pull down the RTS1# pin to change the default value to 0x2E/0x2F. To
enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA
to the index port. Following is an example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87
( enable configuration )
-o 4e aa
( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of
all registers and their default value. Please refer to each device chapter if you want more detail information.
Global Control Registers
Register
0x[HEX]
02
07
20*
21*
23*
24*
25*
26*
27*
28*
28*
29*
29*
2A*
2B*
2B*
2C*
2C*
Global Control Registers
Register Name
Software Reset Register
Logic Device Number Register (LDN)
Chip ID Register
Chip ID Register
Vendor ID Register
Vendor ID Register
I2C Address Register
Clock Select Register
Port Select Register
Multi Function Select 1 Register
Multi Function Select 2 Register
Multi Function Select 3 Register
10Hz Clock Divisor High Byte
10Hz Clock Divisor Low Byte
Multi Function Select 4 Register
10Hz Fine Tune Clock Count High Byte
10Hz Fine Tune Clock Count Low Byte
GPIO0 Enable Register
MSB
--
00
00
00
00
00
00
00
1/0 1/0
-1
00
00
00
11
00
--
--
--
“-“ Reserved or Tri-State
Default Value
----
0000
0100
0100
0110
1101
0000
- 000
0 1/0 0 0
1000
0000
0000
0000
1001
0- - -
----
----
- 000
LSB
-0
00
00
00
01
00
00
11
-0
00
00
11
11
11
10
--
--
00
119
Dec, 2011
V0.12P