F81867 Datasheet, PDF (139/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W LRESET# 03h The MSB of Parallel Port base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W LRESET# 78h The LSB of Parallel Port base address.
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELPRTIRQ
R/W LRESET# 7h Select the IRQ channel for Parallel Port.
DMA Channel Select Register ⎯ Index 74h
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
- Reserved.
0: non-burst mode DMA.
4 ECP_DMA_MODE R/W LRESET# 0
1: enable burst mode DMA.
3
Reserved
-
-
- Reserved.
2-0
SELPRTDMA R/W LRESET# 011 Select the DMA channel for Parallel Port.
PRT Mode Select Register ⎯ Index F0h
Bit
Name
R/W Reset Default
Description
Interrupt mode in non-ECP mode.
7 SPP_IRQ_MODE R/W LRESET# 0 _{0: Level mode.}
1: Pulse mode.
6-3 ECP_FIFO_THR R/W LRESET# 1000 ECP FIFO threshold.
000: Standard and Bi-direction (SPP) mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
011: ECP and EPP 1.9 mode.
2-0
PRT_MODE
R/W LRESET# 010
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
F81867
139
Dec, 2011
V0.12P