F81867 Datasheet, PDF (54/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

6-5
Reserved
R
-
- Reserved
4 PECI_PENDING R/W 5VSB 0 Set this bit 1 to stop monitoring PECI temperature.
3
Reserved
R
-
- Reserved
PECI command to be used by PECI master.
000: PING()
001: GetDIB()
2-0
PECI_CMD
R/W 5VSB 3’h0 ^{010: GetTemp()}
011: RdIAMSR()
100: RdPkgConfig()
101: WrPkgConfig()
others: Reserved
F81867
PECI Master Status Register ⎯ Index 42h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
R
-
2
ABORT_FCS R/WC 5VSB
1 PECI_FCS_ERR R/WC 5VSB
0
PECI_FINISH R/WC 5VSB
- Reserved
This bit is the Abort FCS status of PECI master commands. Write this bit
- _{1 or read this byte will clear this bit to 0.}
This bit is the FCS error status of PECI master commands. Write this bit 1
- _{or read this byte will clear this bit to 0.}
This bit is the Command Finish status of PECI master commands. Write
- _{this bit 1 or read this byte will clear this bit to 0.}
PECI Master DATA0 Register ⎯ Index 43h
Bit
Name
R/W Reset Default
Description
For RdIAMSR(), RdPkgConfig() and WrPkgConfig() command, this byte
7-0
PECI_DATA0
R/W 5VSB 0 represents “Host ID[7:1] & Retry[0]”. Please refer to PECI interface
specification for more detail.
PECI Master DATA1 Register ⎯ Index 44h
Bit
Name
R/W Reset Default
Description
For RdIAMSR() , this byte represents “Processor ID”.
7-0
PECI_DATA1
R/W 5VSB 0 For RdPkgConfig() and WrPkgConfig() , this byte represents “Index”.
Please refer to PECI interface specification for more detail.
PECI Master DATA2 Register ⎯ Index 45h
Bit
Name
R/W Reset Default
Description
For RdIAMSR(), this byte is the least significant byte of “MSR Address”.
7-0
PECI_DATA2
R/W 5VSB
0 ^{For RdPkgConfig() and WrPkgConfig(), this byte is the least significant}
byte of “Parameter”.
Please refer to PECI interface specification for more detail.
54
Dec, 2011
V0.12P