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| F81867 Datasheet, PDF (50/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions | |||
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F81867
TSI Temperature 2 Low Byte â Index E2h
Bit
Name
R/W Reset Default
Description
This is the low byte of Intel temperature interface CPU reading. The
reading is the fraction part of CPU temperature. Bit 0 indicates the error
TSI_TEMP2_LO
R 5VSB
status.
-
0: No error.
7-0
1: Error code.
To access this byte, MCH_BANK_SEL should be set to â0â.
This is the 12th byte of the block read protocol.
I2C_DATA2
R/W 5VSB 8âh00 This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to â1â.
TSI Temperature 2 High Byte â Index E3h
Bit
Name
R/W Reset Default
Description
This is the high byte of Intel temperature interface CPU reading. The
TSI_TEMP2_HI
R 5VSB
- reading is the decimal part of CPU temperature.
To access this byte, MCH_BANK_SEL should be set to â0â.
7-0
This is the 13th byte of the block read protocol.
I2C_DATA3
R/W 5VSB 8âh00 This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to â1â.
TSI Temperature 3 â Index E4h
Bit
Name
R/W Reset Default
Description
TSI_TEMP3
R 5VSB
This is the high byte of Intel temperature interface MCH reading. The
- range is 0~255ºC.
To access this byte, MCH_BANK_SEL should be set to â0â.
7-0
This is the 14th byte of the block read protocol.
I2C_DATA4
R/W 5VSB 8âh00 This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to â1â.
TSI Temperature 4 â Index E5h
Bit
Name
R/W Reset Default
Description
7-0
TSI_TEMP4
R 5VSB
This is the high byte of Intel temperature interface DIMM0 reading. The
- range is 0~255ºC.
To access this byte, MCH_BANK_SEL should be set to â0â.
50
Dec, 2011
V0.12P
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