F81867 Datasheet, PDF (216/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

Port 80 Base Address Low Byte Register ⎯ Offset 11h
Bit
Name
R/W Reset Default
Description
7-0
P80_BASE_L R/W 5VSB 0x00 The 80 port base address low byte.
F81867
7.20.7 Embedded Flash Control (base address 0x1F00, 256 byte)
Control Register1 ⎯ Offset 01h
Bit
Name
R/W Reset Default
Description
7
START_CMD
W
-
- Write 1 to this bit will start a single byte read or single byte write command
6-2
Reserved
-
-
- Reserved
1
IFREN
R/W 5VSB
0 Reserved.
0
FLASH_CMD R/W 5VSB
0 0: Read , 1:Write
Status Register ⎯ Offset 02h
Bit
Name
R/W Reset Default
Description
7-3
Reserved
-
-
- Reserved
1
TIMEOUT_STS
R 5VSB
0 This bit indicates that a single byte write command is timeout and failed.
0
CMD_BUSY
R 5VSB
0 This bit indicates the command is still progressing.
Control Register2 ⎯ Offset 03h
Bit
Name
R/W Reset Default
Description
7-0
ADR_L
R/W 5VSB
0 {ADR_H, ADR_L} is 13-bits address for embedded flash
Control Register3 ⎯ Offset 04h
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
- Reserved
4-0
ADR_H
R/W 5VSB
0 {ADR_H, ADR_L} is 13-bits address for embedded flash
Control Register4 ⎯ Offset 05h
Bit
Name
R/W Reset Default
Description
7-0
WR_DATA
R/W 5VSB
0 This byte is data for single byte write command.
Control Register5 ⎯ Offset 06h
Bit
Name
R/W Reset Default
Description
7-0
RD_DATA
R 5VSB
0 This byte is stores data read by a single byte read command.
216
Dec, 2011
V0.12P