F81867 Datasheet, PDF (188/315 Pages) Feature Integration Technology Inc. – 6 UARTs μSuper IO With 128 Bytes FIFO and Power Saving Functions

Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W 5VSB 00h The MSB of H2E base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W 5VSB 00h The LSB of H2E base address.
F81867
IRQ Channel Select Register ⎯ Index 70h
Bit
Name
R/W Reset Default
Description
7-4
Reserved
-
-
- Reserved.
3-0
SELH2EIRQ
R/W 5VSB 00h Select the IRQ channel for H2E.
7.13 Debug Port Host Side Registers (LDN 0x0F)
Register
0x[HEX]
30
60
61
Register Name
Debug Port I/O Port Enable Register
Base Address High Register
Base Address Low Register
Default Value
MSB
LSB
- - - - - - -0
0 0 0 0 0 0 00
0 0 0 0 0 0 00
Debug Port I/O Port Enable Register ⎯ Index 30h
Bit
Name
R/W Reset Default
Description
7-1
Reserved
-
-
- Reserved
0: disable Debug Port I/O port.
0 DBPORT_IO_EN R/W 5VSB 0
1: enable Debug Port I/O port.
Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_HI R/W 5VSB 00h The MSB of Debug Port base address.
Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
Description
7-0 BASE_ADDR_LO R/W 5VSB 00h The LSB of Debug Port base address.
Debug Port Read Data Register ⎯ Offset + 0x00
Bit
Name
R/W Reset Default
Description
7-0 DBPORT_DATA R 5VSB 00h The reading of μC side register from the debug port.
Debug Port Control Register ⎯ Offset + 0x01
Bit
Name
R/W Reset Default
Description
7 BRK_PRT_TRIG R
-
0 Status of breakpoint trigger.
188
Dec, 2011
V0.12P